1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly to a semiconductor memory device comprising a fixed latency operation mode and/or a fixed burst operation mode.
2. Discussion of Related Art
A conventional semiconductor memory device performing latency and burst operation is designed to perform each of variable operation modes of latency 1, 2, 3, and variable operation modes of burst length 1, 2, 4 and 8.
Here, a latency operation refers to a CAS (column address strobe) latency operation, which is a time delay between the time that effective data is output and the time a read command or signal is applied. CAS latency is given as n clock cycles (where n is an integer). For example, if latency is set at 3, data will be output from a semiconductor device 3 clock cycles after a read command or signal is applied to the semiconductor memory device.
The latency operation of a synchronous dynamic random access memory (SDRAM) is different from that of a double data rate synchronous dynamic random access memory (DDR SDRAM). That is, in case of a SDRAM, if latency is set at n, data is output after being delayed for (nxe2x88x921)tck(clock cycle)+tsac(a delay time from a clock signal generation to the time when effective data is output) after a read command or signal is input. In case of a DDR SDRAM, data is output after being delayed for ntck(clock cycle)+tsac(a delay time from a clock signal generation to the time when effective data is output) after a read command or signal is input.
A burst operation refers to a situation when a column address is input after a row address is input, and data as to continuous column addresses thereafter is output at high speed in synchronization with a clock signal. For example, if burst length is set at 4, a semiconductor memory device outputs 8 data in synchronization with the clock signal if a column address is input from an external source. Typically, if a column address is input once from the external source, the next 7 column addresses are generated internally by a column address generation circuit.
A conventional semiconductor memory device is usually designed to operate at various latency levels and burst lengths. But, in general, if a semiconductor memory device is used in one system, it operates only in one mode. A semiconductor memory device in a conventional computer typically sets CAS latency at 2 and burst length at 4. Therefore, in most cases, there is no need for designing a semiconductor memory device to perform latency at different levels and burst operations at different lengths.
In order to perform various latency and burst operations like the prior semiconductor memory device, a circuit configuration has to be added internally, and also, when testing the device, the test should be performed in all possible cases of operable latency levels and burst lengths. Consequently, the cost of the device is increased and the test time is increased.
Before describing embodiments of semiconductor memory devices of the present invention, a conventional semiconductor memory device will be described.
FIG. 1 is a block diagram showing a configuration of an embodiment of a conventional semiconductor memory device, comprising a memory cell array 10, an address buffer 12, a row address decoder 14, column selection switches 16-1, 16-2, . . . and 16-m, a write data amplifier 18, a sense amplifier 20, a column address decoder 22, a mode setting register 24, a burst address generation circuit 26, a pipeline control signal generation circuit 28, a pipeline circuit 30, a latency enable control signal circuit 32, and a data output driver 34.
A configuration of each block shown in FIG. 1 will now be described in detail. The memory cell array 10 comprises a plurality of memory cells MC connected between n word lines WL1, WL2, . . . , and WLn and m bit line pairs BL1 and BL1B, BL2 and BL2B, . . . ,and BLm and BLmB respectively. The address buffer 12 buffers and outputs an address Ai applied from an external source. The row address decoder 14 generates n word line selection signals WL1, WL2, . . . , and WLn by decoding buffered addresses output from the address buffer 12. The column selection switches 16-1, 16-2, . . . ,and 16-m operate between bit line pairs BL1 and BL1B, BL2 and BL2B, . . . ,and BLm and BLmB and a data input/output line pair IO and IOB by being turned on in response to each of column selection signals Y1, Y2, . . . and Ym. The write data amplifier 18 amplifies and transmits data DI input from the external source to the data input/output line pair IO and IOB.
The sense amplifier 20 amplifies data transmitted from the data input/output line pair IO and IOB. The column address decoder 22 generates the column selection signals Y1, Y2, . . . , and Ym by decoding a burst address PCAj. The mode setting register 24 generates burst length control signals BL1, 2, 4 and 8 and latency control signals CL1, 2 and 3 by receiving address Ai in response to a mode setting control signal PMRS. For setting latency level and burst length, the inputted address Ai is inputted through address input pins (not shown). The burst address generation circuit 26 receives a column address in response to a read signal PC and a clock signal CLK, and generates burst addresses starting from the column address in response to the clock signal CLK, and generates burst addresses in lengths corresponding to the burst length control signals BL1, 2, 4 and 8, and generates a burst length detection signal COSI when the generation of burst addresses is completed. The pipeline control signal generation circuit 28 is enabled in response to the read signal PC and generates pipeline control signals p1, p2 and p3 by delaying the clock signal CLK in response to the latency control signals CL1, 2 and 3. The pipeline circuit 30 delays and outputs a signal from the sense amplifier 20 in response to the pipeline control signals p1, p2 and p3.
The latency enable control circuit 32 generates a latency enable control signal in response to the read signal PC and the burst length detection signal COSI, and delays the latency enable control signal for 1 cycle and 2 cycles in response to the clock signal CLK, and outputs a latency signal, a 1 cycle-delayed latency control signal, or a 2 cycle-delayed latency control signal as a latency enable control signal LA. The data output driver 34 outputs data DO by being enabled in response to the latency enable control signal. The block diagram of an embodiment shown in FIG. 1 is a configuration inputting/outputting 1 bit data, and the number of bits of input/output data can be extended.
FIG. 2 is a block diagram of an embodiment of a burst address generation circuit shown in FIG. 1, which comprises a burst address counter 40, a burst length counter 42, a burst length detector 44 and a counter reset circuit 46. Details of the operation of each block shown in FIG. 2 will now be described.
The burst address counter 40 receives a column address CAi in response to the read signal PC and outputs a burst address PCAj. The burst address counter 40 further generates addresses, counting up from the input column address CAi in response to the clock signal CLK and outputs the addresses as the burst address PCAj. The burst length counter 42 is operated in response to the read signal PC and generates a signal CNT, counting in response to the clock signal CLK. The burst length detector 44 generates a burst length detection signal COSI if the burst length control signal BL1, 2, 4 and 8 coincides with the signal CNT by comparison. The counter reset circuit 46 is enabled in response to the read signal PC, and generates a reset signal PCAR. The reset signal PCAR is enabled in response to the read command or signal PC and disabled when the burst length detection signal COSI is generated. Then, the generated reset signal PCAR is used to reset counters 40 and 42.
FIG. 3 is a block diagram of an embodiment of the pipeline control signal generation circuit shown in FIG. 1, illustrating buffers 50 and 52, and logic and delay circuits 54 and 56. Details of the operation of each block shown in FIG. 3 will now be described.
A buffer 50 generates a clock signal PCLK by buffering a clock signal CLK applied from the external source. A buffer 52 is enabled in response to the read signal PC and generates a pipeline control signal p3 by buffering the clock signal CLK applied from the external source. The generated pipeline control signal p3 at that time is a signal, which is generated by buffering the clock signal CLK applied from the external source after the read signal PC is generated. A logic and delay circuit 54 is enabled in response to the read signal PC, and generates a logic low level pipeline control signal p1 by delaying the clock signal CLK in response to a latency control signal CL3, and generates a logic high level pipeline control signal p1 in response to the latency control signal CL1 and CL2. A logic and delay circuit 56 is enabled in response to the read signal PC, and generates a logic low level pipeline control signal p2 by delaying the pipeline control signal p3 in response to the latency signal CL3, and generates a logic high level pipeline control signal p2 in response to the latency control signal CL1.
According to the latency control signal generation circuit shown in FIG. 3, the logic and delay circuits 54, 56 generate logic high level latency control signals p1 and p2 when the latency control signal CL1 is generated. The buffer 52 generates the pipeline control signal p3 by buffering the clock signal CLK applied from the external source. If the latency control signal CL2 is generated, the logic and delay circuit 56 generates the logic high level latency control signal p2, and the buffer 52 and the logic and delay circuit 54 generate pipeline control signals p3 and p1 respectively.
FIG. 4 is a configuration of an embodiment of a pipeline circuit 30 shown in FIG. 1, which comprises three D flip flops 60, 62 and 64. The operation of the circuit shown in FIG. 4 will now be described.
If latency CL is set at 1, the pipeline control signals p1 and p2 are fixed at logic high level, and D flip flops 60 and 62 transmit its own input signal IN as it is, and the D flip flop 64 latches an output signal of the D flip flop 62 in response to the pipeline control signal p3 and generates an output signal OUT. That is, the input signal IN is delayed one cycle and then outputted.
If latency is set at 2, the pipeline control signal p2 is fixed at logic high level, and the D flip flop 62 transmits its own input signal as it is, the D flip flop 60 latches and outputs its own input signal IN in response to the pipeline control signal p1. The D flip flop 64 latches the output signal of the D flip flop 62 in response to the pipeline control signal p3 and outputs an output signal OUT. That is, the input signal IN is delayed two cycles and then outputted by the D flip flops 60 and 64.
If latency is set at 3, all pipeline control signals p1, p2, and p3 are generated (not fixed xe2x80x9chighxe2x80x9d), and the D flip flops 60, 62 and 64 latches its own input signal, respectively, and thus generate the output signal OUT by delaying the input signal IN three cycles in response to the pipeline control signals p1, p2 and p3.
FIG. 5 is a configuration of an embodiment of the latency enable control signal generation circuit 32 shown in FIG. 1, which comprises a set-reset (SR) flip flop 70, D flip flops 72 and 74, and a multiplexer 76. The operation of each block shown in FIG. 5 will be described as follows.
The SR flip flop 70 is enabled in response to the read signal PC and generates a first latency signal LA1, which is reset in response to the burst length detection signal COSI. The D flip flop 72 generates a second latency signal LA2 by delaying the first latency signal LA1 one cycle in response to the clock signal CLK. The D flip flop 74 generates a third latency signal LA3 by delaying the second latency signal LA2 one cycle in response to the clock signal CLK. The multiplexer 76 generates the first, the second, and the third latency signals LA1, LA2, and LA3 as a latency enable signal LA in response to each of the latency enable control signals CL1, CL2, and CL3.
FIG. 6 is a timing diagram illustrating the operation of an embodiment of the semiconductor memory device shown in FIG. 1, which is for illustrating the operation in case that latency CL is set at 3 and the burst length BL at 4. The operation of the semiconductor memory device will be described as follows using the timing diagram shown in FIG. 6.
If an address Ai is applied together with a mode register setting control command or signal PMRS, the semiconductor memory device stores the address Ai in the mode setting register 24 responding to the mode register setting control command or signal PMRS, and generates latency signals CL1, CL2, and CL3 and burst length control signals BL1, BL2, BL4, and BL8 internally. Then, the applied address Ai is a signal not for accessing the memory cell array 10 but for setting the operation mode.
If a row address RA is applied together with an active command or signal ACT two cycles after the mode register setting control command or signal PMRS is applied, the semiconductor memory device selects one word line among n word lines WL1, WL2, . . . , and WLn of the memory cell array 10.
If a column address CA is applied together with the read command or signal RD three cycles after the active command or signal ACT is applied, the semiconductor memory device generates a read signal PC internally. And, the burst address generation circuit 26 generates four burst addresses PCAj starting from the buffered column address outputted from the address buffer 12 in response to the burst length control signal BL4, and generates a burst length detection signal COSI if the generation of burst addresses is ended. The column address decoder 22 generates column selection signals Y1, Y2, Y3 and Y4 in sequence by decoding the address PCAj. The timing diagram of FIG. 6 is shown under the assumption that the burst address is an address increasing from the inputted column address in sequence.
The column selection switches 16-1, 16-2, . . . , and 16-m transmit data of bit line pairs BL1 and BL1B, BL2 and BL2B, . . . , and BLm and BLmB to the data input/output line pair IO and IOB respectively in response to each of column selection signals Y1, Y2, Y3 and Y4. If the read signal PC is generated, the counter reset signal PCAR is enabled, and if the generation of column selection signals Y1, Y2, Y3 and Y4 is ended, the counter reset signal PCAR is disabled. If generation of the column selection signals Y1, Y2, Y3 and Y4 is ended, the burst length detection signal COSI is generated. The latency enable control signal generation circuit 32 generates a first latency signal LA1, which is enabled in response to the read signal PC and is disabled in response to the burst length detection signal COSI, and generates a third latency signal LA3 by delaying the first latency control signal LA1 two cycles in response to the clock signal CLK. It also generates the third latency signal LA3 as a latency enable control signal LA1 in response to the latency control signal CL3. The pipeline control signal generation circuit 28 generates pipeline control signals p1, p2 and p3 in response to the latency control signal CL3.
The pipeline circuit 30 generates a first output signal FDO in response to the pipeline control signal p1, and generates a second output signal SDO in response to the pipeline control signal p2, and generates a signal OUT in response to the pipeline control signal p3. The generated signal OUT at that time is generated as data output signals D01, D02, D03, and D04 by being delayed through the data output driver 34. With this method, the operation of the semiconductor memory device whose latency is fixed at 3 and burst length at 4 is performed.
FIG. 7 is a timing diagram showing the operation of another embodiment of the semiconductor memory device shown in FIG. 1, illustrating the operation in case that CAS latency CL is set at 2 and burst length BL at 4. The operation of the semiconductor memory device will be described as follows using the operation timing diagram shown in FIG. 7.
The operation time until the read signal PC and the column selection signals Y1, Y2, Y3, and Y4 are generated and data is outputted from bit line pairs BL1 and BL1B, BL2 and BL2B, . . . , and BLm and BLmB to the data input/output line pair IO and IOB in response to each of the column selection signals Y1, Y2, Y3, and Y4, after the read command or signal RD is applied, and the operation time until the burst length detection signal COSI and the counter reset signal PCAR are generated, are the same time period as shown in timing diagram of FIG. 6.
The latency enable control signal generation circuit 32 generates a second latency signal LA2 (shown as latency enable control signal LA) by delaying a first latency signal LA1 one cycle in response to the clock signal CLK. The pipeline control signal generation circuit 28 generates a pipeline control signal p1 by delaying the clock signal CLK, being enabled in response to the read signal PC, and the pipeline circuit 30 outputs data FDO in response to the pipeline control signal p1 by receiving data from the sense amplifier 20. And, the pipeline circuit 30 outputs data FDO as data SDO in response to the xe2x80x9chighxe2x80x9d level pipeline control signal p2, and outputs data SDO as data OUT in response to the pipeline control signal p3. The data OUT generated at that time is output as data DO by being delayed through the data output driver 34. With this method, the operation of the semiconductor memory device whose latency CL is fixed at 2 and burst length at 4 is performed.
The above-described prior semiconductor memory device, which comprises the mode setting register 24, the burst address generation circuit 26, the pipeline control signal generation circuit 28, the pipeline circuit 30, and the latency enable control signal generation circuit 32 is incapable of performing the operation in a case where CAS latency CL is set at 3 and burst length BL at 8. In addition, the prior semiconductor memory device increases test time and thus reduces the productivity because test is required for all modes of operations. And, the prior semiconductor memory device should perform the operation of applying the mode register setting command or signal before an active command or signal is applied to set latency and burst length during operation.
The present invention is directed to a semiconductor memory device that comprises a simple circuit configuration to provide a fixed latency and/or burst length mode of operation.
A semiconductor device according to the present invention also provides a reduction in test time by providing a fixed latency and/or burst length mode of operation.
According to an embodiment of the present invention, a semiconductor memory device comprises a memory cell array, burst address generation means to generate a burst address and a burst length detection signal by receiving an address, pipeline means to delay and output data that is read from the memory cell array, latency enable control signal generation means to generate a latency enable control signal in response to a read command or signal and the burst length detection signal, and data output means to output data from the pipeline circuit in response to the latency enable control signal. The burst address generation means generates burst addresses according to a fixed burst length, which is a time until data, which is read from the memory cell array in response to the burst address after the read command or signal is applied, is outputted through the pipeline circuit and the data output circuit. The burst length is fixed at n (n is integer), indicating n times as long as a cycle of a clock signal applied from the external source.
According to another embodiment of the present invention, a semiconductor memory device comprises a memory cell array, a mode setting register to store a mode setting command or signal applied from the external source to set a burst length and to generate a burst length control signal, burst address generation means to generate a burst address and a burst length detection signal in response to the burst length control signal by receiving an address, pipeline means to delay and output data that is read from the memory cell array, latency enable control signal generation means to generate a latency enable control signal in response to a read command or signal and the burst length detection signal, and data output means to output data from the pipeline circuit in response to the latency enable control signal. A time is counted until data, which is read from the memory cell array in response to the burst address after the read command or signal is applied, is outputted through the pipeline circuit and the data output circuit. The time is fixed at n (n is integer), indicating n times as long as a cycle of a clock signal applied from the external source.
According to a further embodiment of the present invention, a semiconductor memory device comprises a memory cell array, a mode setting register to store a mode setting command or signal applied from the external source to set latency and to generate a latency control signal, burst address generation means to generate a burst address and a burst length detection signal of fixed length by receiving an address, pipeline means to delay and output data that is read from the memory cell array in response to the latency control signal, latency enable control signal generation means to generate a latency enable control signal in response to a read command or signal, the burst length detection signal and the latency control signal, and data output means to output data from the pipeline circuit in response to the latency enable control signal.
Therefore, according to a semiconductor memory device of the present invention, a circuit configuration is simplified and the product cost is reduced in terms of fixing latency and/or burst length, and there is no necessity for further setting latency CL and burst length BL during operation.
Also, because there is no necessity for testing varying CAS latency CL and burst length BL during test in the semiconductor memory device of the present invention, the test time is reduced, and accordingly the productivity is improved.